The present invention relates to integrated circuit devices and methods of forming integrated circuit devices, and more particularly to bipolar junction transistors and methods of forming bipolar junction transistors.
Attempts to develop bipolar junction transistors (BJTs) having higher operating speeds than conventional silicon-based bipolar junction transistors have led to the development of GaAs-based BJTs and heterojunction bipolar junction transistors (HBTs). However, the use of materials such as GaAs and the formation of HBT devices typically increases the complexity and cost of fabricating BJTs.
To address these limitations associated with GaAs-based BJTs and HBTs, continuing attempts have been made to develop silicon-based BJTs having improved electrical characteristics (e.g., higher operating speeds). For example, as described in U.S. Pat. No. 5,286,996 to Neudeck et al., entitled xe2x80x9cTriple Self-Aligned Bipolar Junction Transistorxe2x80x9d, self-alignment techniques have been developed to reduce fabrication complexity and reduce reliance on critical photolithographically defined masking and patterning steps. Recent attempts to develop self-aligned BJTs have also included the design of vertical and lateral scaling and base resistance reduction techniques. For example, a vertical scaling technique is disclosed in an article by Takashi Uchino et al., entitled xe2x80x9c15-ps ECL/74-GHz fT Si Bipolar Technologyxe2x80x9d, IEDM Technical Digest, pp. 67-70 (1993). A lateral scaling technique is also disclosed in an article by A. Pruijmboom et al., entitled xe2x80x9c18ps ECL-Gate Delay in Laterally Scaled 30 Ghz Bipolar Transistorxe2x80x9d, IEDM Technical Digest, pp. 825-828 (1994). A base resistance reduction technique is disclosed in an article by C. Yoshino et al., entitled xe2x80x9cA 62.8 GHz fmax LP-CVD Epitaxially Grown Silicon Base Bipolar Transistor with Extremely High Early Voltage of 85.7Vxe2x80x9d, 1995 Symposium on VLSI Technology, Technical Digest, pp. 131-132 (1995). Unfortunately, the techniques disclosed in these articles may not be useful in developing BJTs having both high cutoff frequency fT and high maximum oscillating frequency fmax.
In order to simultaneously improve the cutoff frequency and the maximum oscillating frequency of a BJT, it may be necessary to optimize the diffusion profile of extrinsic base region dopants diffused from a polysilicon base electrode. For example, if the extrinsic base region dopants are diffused to define a large extrinsic base region, the base-collector junction capacitance may increase and limit the cutoff frequency. However, if the extrinsic base region dopants are diffused to define a small extrinsic base region, the base resistance may increase to a level that is too high.
Other techniques for forming BJTs are disclosed in an article by Mamoru Ugajin et al., entitled xe2x80x9cVery-High fT and fmax Silicon Bipolar Transistors Using Ultra-High-Performance Super Self-Aligned Process Technology for Low-Energy and Ultra-High-Speed LSI""sxe2x80x9d, IEDM Technical Digest, pp. 735-738, (1995). In this article, emphasis is placed on reducing lateral dimensions in order to reduce base-collector junction capacitance and base resistance and increase fT. The fmax of the BJT disclosed in this article was also reported as being twice as large as the fmax disclosed in an article by Chikara Yamaguchi et al., entitled xe2x80x9c0.5-um Bipolar Technology Using a New Base Formation Method: SST1Cxe2x80x9d, IEEE Proceedings of the Bipolar Circuits and Technology Meeting, pp. 63-66, (1993).
FIGS. 1-2 illustrate a conventional bipolar junction transistor, as described in the aforementioned Ugajin et al. article. In particular, FIGS. 1-2 illustrate a bipolar junction transistor having an N+ epitaxial intrinsic collector region 13 that is formed on a buried extrinsic collector layer 11 within a P-type substrate 10. Field oxide isolation regions 15 are also formed in the substrate 10, as illustrated. Electrical isolation is also provided by a plurality of trench-based isolation regions that include an oxide layer 19 lining the trenches 17 and highly-doped channel-stop regions 18 at the bottoms of the trenches. The trench-based isolation regions also include polysilicon regions 21 that act as floating field rings. An N+ polysilicon collector contact 33 is also provided on the buried layer 11 and P+ polysilicon base electrodes 23 are provided on the field oxide isolation regions 15. The illustrated bipolar junction transistor also includes first and second interlayer insulating layers 25 and 37, an emitter electrode 31, intermediate emitter, base and collector contacts 51, 53 and 55 (which may comprise tungsten) and emitter, base and collector wiring layers 52, 54 and 56.
Referring now to FIG. 2, region A within FIG. 1 is illustrated in greater detail. As illustrated by FIG. 2, the bipolar junction transistor also includes an emitter region 41, an intrinsic base region 43 and an extrinsic base region 42. The extrinsic base region 42 may be formed as a self-aligned region by diffusing dopants from the polysilicon base electrode 23 into the intrinsic collector region 13. As illustrated, the width of the extrinsic base region 42 may be dependent on the width W2 of the contact formed between the polysilicon base electrode 23 and the intrinsic collector region 13. The first interlayer insulating layer 25 may comprise silicon nitride and sidewall spacers 29 may be formed on sidewalls of the polysilicon base electrode 23, as illustrated. The polysilicon emitter electrode 31 may also be formed in the opening 27 (having a width W1) between the sidewall spacers 29. Emitter region dopants can also be diffused from the emitter electrode 31 into the intrinsic base region 43, to define a self-aligned emitter region 41. Unfortunately, because the patterning of the polysilicon base electrodes 23 typically requires a critical photolithographically defined masking and patterning step, the width of the opening W1 and therefore the width of the intrinsic base region 43 and emitter region 41 may be relatively large. Such large dimensions may result in relatively large parasitic capacitance and may limit integration and the maximum oscillating frequency fmax.
Thus, notwithstanding the above-described bipolar junction transistors and methods of forming bipolar junction transistors, there continues to be a need for more highly integrated bipolar junction transistors having improved electrical characteristics.
It is therefore an object of the present invention to provide bipolar junction transistors having improved electrical characteristics and improved methods of forming bipolar junction transistors.
It is another object of the present invention to provide highly integrated bipolar junction transistors and methods of forming highly integrated bipolar junction transistors.
It is still another object of the present invention to provide methods of forming bipolar junction transistors that utilize self-alignment techniques to more accurately control the dimensions of critical regions within the transistor.
These and other objects, advantages and features of the present invention are provided by bipolar junction transistors that utilize trench-based base electrodes and lateral base electrode extensions to facilitate the use of preferred self-alignment processing techniques. According to one embodiment of the present invention, a bipolar junction transistor is provided that includes an intrinsic collector region of first conductivity type (e.g., N-type) in a semiconductor substrate. A trench (e.g., ring-shaped trench) is also provided in the substrate. This trench extends adjacent the intrinsic collector region. According to a preferred aspect of the present invention, a base electrode of second conductivity type (e.g., P-type) is provided in the trench and a base region of second conductivity type is provided in the intrinsic collector region. This base region is self-aligned to the base electrode and forms a P-N rectifying junction with the intrinsic collector region. An emitter region of first conductivity type is also provided in the base region and forms a P-N rectifying junction therewith. To reduce lateral dimensions and reliance on critical photolithographically defined masking steps, the base electrode is formed to have a lateral base electrode extension that extends along a surface of the substrate. When formed, both the base region and emitter region are self-aligned to the base electrode extension. A trench insulating layer is also disposed in the trench, between the base electrode and the intrinsic collector region. The base region is also configured as an extrinsic base region of second conductivity type that is self-aligned to the base electrode and an intrinsic base region of second conductivity type that is self-aligned to a sidewall of the base electrode extension. The emitter region is also preferably self-aligned to the sidewall of the base electrode extension.
According to another embodiment of the present invention, preferred methods of forming bipolar junction transistors include the steps of forming a trench in a semiconductor substrate having an intrinsic collector region of first conductivity type therein and then forming a base electrode of second conductivity type in the trench. A base region of second conductivity type and an emitter region of first conductivity type are both formed in the intrinsic collector region in a self-aligned manner. In particular, the preferred self-alignment technique utilizes steps of forming an electrically insulating masking layer as a composite of a nitride layer and an oxide layer, on the semiconductor substrate, and then etching the semiconductor substrate to define the trench, using the electrically insulating masking layer as an etching mask. After the trench has been formed, the nitride layer (or oxide layer) is selectively etched to define a lateral recess within the electrically insulating masking layer. The base electrode is then formed by depositing a layer of polysilicon of second conductivity type in the trench and in the lateral recess. Dopants of second conductivity type are then diffused from the base electrode into the intrinsic collector region, to define an extrinsic base region therein. Based on this sequence of steps, the extrinsic base region becomes self-aligned to the lateral recess within the electrically insulating masking layer and the dimensions of this lateral recess can be defined by carefully controlled etching techniques instead of critical photolithographic alignment techniques. The emitter region is also self-aligned to the base electrode. The emitter region is preferably formed by etching the electrically insulating masking layer, using the base electrode as an etching mask and then forming an electrically insulating sidewall spacer on a sidewall of the base electrode. A polysilicon emitter electrode of first conductivity type is then formed on the electrically insulating sidewall spacer. Dopants of first conductivity type are then diffused from the polysilicon emitter electrode into the intrinsic collector region to define the emitter region.